You should see the following printout in the Transcript window Type "run 2000ns" to run the simulation for 2000ns.Type "vsim test" to start simulating the test module.Output from the compiler is displayed in the Type "vlog sources/lab2_1.v" to compile the verilog file youĭownloaded above.Type "vlib work" to set up the simulator's working.The folder where you want to run your lab, e.g. "Transcript" where you can type in commands and see various At the bottom of the Modelsim window there's a frame labeled.Start Modelsim (either by typing "vsim &" or from Xilinx ISE).Feel free to useĮither approach for this part of the lab.
#Modelsim transcript how to#
With Modelsim for details on how to do this. Xilinx ISE toolkit - see the labkit documentation Simulating The steps below describe how to use our Verilog simulator ModelsimĪs a standalone application. It is good to be organized and put all your labs in separate folders - e.g. The link and select "Save As" (or "Save Link As"), and specify a destination. If you have bash, add the the following to ~/.bashrc.mineĪlias ise="tcsh -c 'source /mit/6.111/tools.tcsh ise'"Īlias vsim="tcsh -c 'source /mit/6.111/tools.tcsh vsim'"Īlias impact="tcsh -c 'source /mit/6.111/tools.tcsh impact'" If you have tcsh, add the following to ~/.cshrc.mine Most accounts created after 2009 use bash. It should be either tcsh or bash (the name of your shell program). Look at what is listed under the CMD column. You can setup your environment permanently and avoid adding the locker and set up command each time you loginīy customizing your configuration file. To run Modelsim type: vsim & (the '&' allows you to keep typing in the terminal) This will set up the 6.111 tools (Modelsim, Xilinx ISE and Impact). This will add the 6.111 locker, allowing you to access various files important for 6.111. This will ensure that the shell program you're running is cshell, which we know to have working scripts for.
#Modelsim transcript password#
Username and password are your standard Athena user name and password. Log into one of the Athena workstations in the Digital Lab.In this exercise you'll design a Verilog module that implements a labkit.v, top-level module for labkit projects.Simulating with Modelsim, part of the Labkit documentation.Getting Started, part of the Labkit documentation.Goal: implement simple circuits in Verilog and run ModelSim fromĬommand line and within ISE download and run a sample circuit on the